TCP conventional congestion control
treats packet loss as a signal of network overload, but this assumption breaks down on modern networks with shallow-buffered switches and wireless links. BBR, developed a…
Memories
Random Memories for Random People
Things I learned and wanted to keep — a black hole with a 94-year orbit, a library that leaked keys, a layer of rock under Bermuda. Short, sourced-by-curiosity, and sorted for you automatically.
- Memories
- 34
- Topics
- 8
- Since
- Aug 2026
- Latest
- Aug 16
The serverless abstraction
hides servers so completely that many developers forget cold starts exist until latency spikes in production. What appears as pure function execution is actually a contai…
CPU clock speeds
have been stuck near 3-4 GHz for nearly two decades, not because engineers gave up, but because physics intervened. The power density at higher frequencies would melt the…
- 4 ghz
AMD's 3D V-Cache
stacks memory vertically on top of CPU cores using through-silicon vias, turning a planar problem into a spatial one. It is the hardware equivalent of realizing you canno…
A modern SSD
's random read latency is now lower than DRAM access latency was in the year 2000. The storage hierarchy has quietly inverted in places: what was once hopelessly slow is …
Apple M-series chips
The Apple M-series chips are not impressive because they are fast; they are impressive because they made the memory bus disappear. By putting DRAM on the same package as …
RISC-V
's entire instruction set manual fits in 236 pages, while x86 documentation spans thousands and requires a license to implement. It is the first major CPU architecture de…
brain-inspired nanoelectronic chip
A brain-inspired nanoelectronic chip demonstrated in 2026 could reduce AI energy consumption by roughly 70% compared to conventional GPUs. The breakthrough uses a modifie…
- 70 %
The TCP congestion window
is a distributed rate limiter that uses packet loss as its only feedback signal. Every TCP connection on the internet is participating in a global control loop that no si…
modern SSD
A modern SSD's random read latency is now lower than DRAM access latency was in the year 2000. This means the storage hierarchy has partially inverted—what was once consi…